Concomitant with the growth and expansion of satellite communication networks has been the need for filtering schemes for reducing noise and cross talk within the communication channel. Problems with narrowband satellite communication links include the significant amount of Gaussian noise encountered, the need to reduce or prevent intersymbol interference within the channel and the need to reduce cross talk from adjacent channels. For the purpose of overcoming these problems, satellite communication modems have been configured to include analog filtering schemes that typically have a Bessel function characteristic and are classically configured to as closely as possible simulate an infinite impulse response. Unfortunately, these schemes are extremely complicated and difficult to implement, requiring an inordinate amount of hardware, thereby increasing the cost of the system.
With the increasing development of semiconductor technology and sophisticated data processing techniques, proposals for reducing analog hardware complexity by replacing conventional analog filtering schemes with digital implementations have become particularly attractive. Typically, the digital filter is configured to determine the values of successive samples of a filtered output signal by forming the sums of algebraic products of successive samples of an input signal. Namely, the filter typically performs the operation so that the output sample Y.sub.i of a sampling instant i may be expressed as ##EQU1## where .alpha. represents a multiplication coefficient and x.sub.i-k represents data samples. Filters of this type are referred to as non-recursive digital filters.
Conventionally, in order to perform the filtering algorithm calculations, digital filters have been implemented in the form of a plurality of delay shift register stages, multipliers (each providing a weighing coefficient) and an adder or accumulator coupled to the outputs of the multiplier stages. In addition, there have been proposed schemes which employ programmable read-only memories, programmed with weighting coefficients, in place of the multiplier stages, with a separate adder or accumulator provided at the output of the respective ROM. For an overview of digital filtering schemes of the type mentioned above, whether they be of the recursive or non-recursive type, attention may be directed to U.S. Pat. Nos. 3,777,130; 3,737,636; 3,794,816; 3,822,404; 3,914,588; and 4,146,931, as well as an article by Peled and Liu entitled "A new Hardware Realization of Digital Filters", IEEE Transactions on Acoustics, Speed and Signal Processing, Vol. 22, no. 6, December, 1974 pp. 456-461 and an article by S. L. Freeny entitled "Special-purpose Hardware for Digital Filtering", Proceedings of the IEEE, April 1975, pp 633-648.
Unfortunately, most classical digital filtering schemes, including approaches such as those described in the above-referenced literature, have been aimed at meeting a particular frequency response. Techniques such as window functions, etc., have been devised to improve the frequency characteristics, with some degradation in the time domain response. Brute force hardware implementations, for simulating an infinite impulse response, are extremely difficult to achieve and require an inordinate amount of hardware, as mentioned previously.